1. Field of the Invention
This invention relates to a memory circuit which requires periodic refresh operations, such as dynamic random access memory, and further relates to a memory circuit in which refresh operations are executed automatically without requiring a refresh command from outside, and which is capable of high-speed internal execution of operating commands from outside. This invention also relates to an integrated circuit device, which, in addition to external commands, is able to automatically generate and execute commands internally.
2. Description of the Related Art
Dynamic random access memory (DRAM) is widely used as large-capacity memory. Because DRAM is volatile memory, refresh operations are necessary.
FIG. 1 is a configurational view of a conventional memory circuit. The conventional memory circuit has a clock buffer 10 for input of an external clock signal CLK and generation of an internal clock signal CLK1 in sync with this; a command decoder 11 for input of commands in sync with the internal clock signal CLK1; an address buffer 12 for input of addresses; and a data input/output buffer 13 for data input and output. In addition, a control circuit 14 controls operations of a memory core 15 in response to commands CMD input by the command decoder 11. Operations of the memory core are also controlled in sync with the internal clock signal CLK1.
Such clock-synchronous DRAM (SDRAM) has, as refresh operations, auto-refresh and self-refresh. Auto-refresh is a refresh operation which is performed periodically between normal read and write operations, and is executed by means of an auto-refresh command supplied from outside. That is, when an auto-refresh command is input from outside, the command decoder 11 generates an auto-refresh command AR1, and in response to AR1 the refresh control circuit 16 generates an internal refresh command REF. By means of this internal refresh command REF, the control circuit 14 controls the refresh operation. A selector 18 selects the address from the refresh address counter 17 and outputs the address to the address latch circuit 19.
On the other hand, self-refresh is a refresh operation in which the memory device itself executes the refresh operation while in the power-down mode state, in response to refresh timing automatically generated by an internal oscillator OSC. In the power-down mode state, no commands (read or write) are supplied from outside, and so the refresh control circuit 16 generates an internal refresh command REF in response to refresh timing generated with arbitrary timing. Thus, the control circuit 14 controls the refresh operation.
In this way, commands are supplied from outside while in the normal operating state, and refresh commands are also supplied from outside and refresh operations executed in response. While in the power-down state, no commands are supplied from outside, and so refresh timing is automatically generated internally and refresh operations are executed.
In this way, in conventional memory circuits the memory controller which controls the memory circuit must control the refresh timing during the interval of the normal operating state. That is, the memory controller is equipped with a timer, and must issue auto-refresh commands to the memory circuit each time the refresh timing occurs. Hence, a problem with the memory controller is the complexity of memory circuit control.
In conventional memory circuits, the control circuit 14 executes control in response to read and write commands supplied in sync with the clock signal. Here, if the control circuit 14 is executing the previous internal operation, the next internal operation is executed in response to the newly supplied command, regardless of previous internal operations. Memory circuits have also been proposed in which, if during execution of the previous internal operation a new command is supplied from outside, that command is refused.
In the above latter case, refusal of a command from the memory controller is undesirable, and so memory circuits generally execute internal operations as-is in response to supplied commands, as in the former case. Hence, in the normal operating state, if a refresh command is issued autonomously within the memory circuit and refresh operations are executed, a command supplied during these operations may disturb the refresh operation. And if, as in the latter case, a supplied command is refused, control by the memory controller becomes even more complex.
Hence, one object of this invention is to provide a memory circuit capable of automatically executing refresh operations without receiving refresh commands from the memory controller.
Another object of this invention is to provide a memory circuit which, in normal operation, can automatically execute refresh operations without requiring refresh commands from outside, and which can also rapidly execute internal operations in response to normal commands from outside.
Yet another object of this invention is to provide an integrated circuit device capable of automatically issuing internal commands in addition to receipt of externally supplied commands, and of executing internal commands without disturbing operations corresponding to external commands.
In order to achieve the above objects, in a first aspect of this invention, an integrated circuit device comprises a first circuit which receives commands in sync with a clock signal and which internally generates a first internal command, and a second circuit which internally generates a second internal command in a prescribed cycle. The internal circuit executes internal operations in accordance with the first internal command through clock-synchronous operations, and when a second internal command is issued, sequentially executes internal operations corresponding to the second internal command and internal operations corresponding to the first internal command through clock-asynchronous operations.
In a more preferred embodiment, the above integrated circuit device is a memory circuit which requires refresh operations; the above first internal command is a read or a write command; the above second internal command is a refresh command; and the internal circuit is a memory control circuit. That is, in this embodiment, in the normal state the memory control circuit executes control operations corresponding to the first internal command through clock-synchronous operations, in accordance with commands received in sync with the clock signal. When a refresh command is generated internally as the second internal command, the memory control circuit, in clock-asynchronous operation, sequentially executes control operations corresponding to this refresh command and the first internal command. When internal operation cycles finally catch up to external operation cycles, the memory control circuit again executes control operations for the first internal command through clock-synchronous operations.
In another preferred embodiment, the integrated circuit device further comprises an internal clock generation circuit which generates a first internal clock signal in sync with an external clock signal and a second internal clock signal faster than the external clock signal. The internal circuit executes an internal operation corresponding to the first internal command in sync with the first internal clock signal during a normal state, and executes internal operations corresponding to the first internal command and internal operations corresponding to the second internal command in sync with the second internal clock signal when the second internal command is generated.
The first aspect of the invention can be applicable to asynchronous memory circuit. In this case, a specification of the memory circuit defines a minimum external command cycle according to which external commands are permitted to be supplied. And a memory controller has an internal operation cycle shorter than the minimum external command cycle. The memory control circuit executes an internal operation in response to the external command during a normal state, and executes internal operations continuously according to the internal operation cycle.
A second aspect of this invention is a clock-synchronous integrated circuit device having, for every M external operation cycles (Mxe2x89xa72), N internal operation cycles, where N is greater than M (M less than N less than 2M). For M external operation cycles, at most M internal operation cycles corresponding to M external commands, and at least one internal operation cycle corresponding to an internal command and not to an external command, are assigned. That is, by making internal operation cycles slightly shorter than external operation cycles, it is possible to execute internal commands which may occur within expanded operation cycles consisting of M external operation cycles.
In a more preferred embodiment of the above second aspect, application is to a memory circuit requiring refresh operations. In this case, when a refresh command is generated internally during expanded operation cycles consisting of M operation cycles, (Nxe2x88x92M) internal operation cycles are utilized to execute the refresh operation. These (Nxe2x88x92M) cycles are the difference during expanded operation cycles between the number of internal operation cycles N and the number of external operation cycles M. However, by holding the latency from the input of the external command until read data output to several clock cycles, it is possible to continuously output read data, to an external memory controller, corresponding to continuous external commands.
In the memory circuit of the above preferred embodiment, an internal clock generation circuit is provided which generates, during an expanded operation cycle consisting of M external clock cycles, N internal clocks. An external command is input in sync with the external clock signal (or after waiting for a prescribed phase difference), and the internal command is generated in sync with the internal clock signal. Read data is output from the memory core in sync with the delayed internal clock signal, and is output from the data output terminal in sync with the external clock signal. Similarly, write data is input from the data input terminal in sync with the external clock signal, and is input to the memory core in sync with the internal clock signal. Hence, the phase difference between the external clock signal and internal clock signal is absorbed by the command and data input/output circuit units.
In the other preferred embodiment of the above second aspect, application is similarly to a memory circuit in which refresh operations are required. In this case, when a refresh command is generated internally during an expanded operation cycle consisting of M operation cycles, (Nxe2x88x92M) internal operation cycles are utilized to execute the refresh operation. Further, the refresh operation can be divided into a plurality of internal operation cycles and executed. Thus, the latency (access time) from input of the external command until output of the read data can be shortened, and high-speed operation can be ensured.
In another preferred embodiment, when refresh operations are divided into operations involving word-line driving and operations involving writing to memory cells, when the refresh address during a refresh operation (row address) and the address of subsequent read or write operations (row address) coincide, data read out and held during the first half of the refresh operation is used as readout data for subsequent read or write operations. Thus, even though data in memory cells is destroyed during the first half of the refresh operation, there are no impediments to subsequent operations.
A third aspect of this invention is characterized in that, when in the above second aspect the external clock signal controlling input of external commands has a shorter cycle than the external operation cycle, a second internal operation cycle is generated according to the external commands input in sync with the external clock signal. Hence, when this third aspect is applied to a memory circuit, the refresh command generation circuit generates refresh commands according to the state of input of external commands.
By means of this third aspect, even in the case of an integrated circuit device or memory circuit installed in a high-speed clock system, a second internal operation cycle can be autonomously generated and executed.